The present invention relates to a random access memory (RAM) and, more particularly, a pre-charge circuit for bit lines of RAM.
The present inventor has developed a RAM circuit as disclosed in Zibu, U.S. Pat. No. 4,112,506 issued Sept. 5, 1978, entitled "RANDOM ACCESS MEMORY USING COMPLEMENTARY FIELD EFFECT DEVICES", the disclosure of which is incorporated herein by reference.
FIGS. 1 through 3 and 6 disclose the prior art as disclosed in that patent. With reference to FIG. 1, which is simplified from the patent figure the prior art circuit mainly comprised an inverter circuit I.sub.n1 and switching elements T.sub.N3 and T.sub.P3 connected between a -V source voltage and the ground. Writing timing signals W and Ware applied to the switching elements T.sub.N3 and T.sub.P3.
FIG. 2 shows a timing chart of signals occurring in connection with the circuit of FIG. 1.
In the prior art circuit as shown in FIG. 1, conventionally, a bit line L was connected to a plurality of RAM cells so that the inherent wiring capacitance Cb of the bit line L was very greater than that of point A within each of the RAM cells. This increased the level of row address signals R.sub.OW to make a transmission gate TR conductive. Just after any RAM cells were selected, the voltage in the point A in one of the RAM cells selected was as follows: ##EQU1## where with reference to FIG. 3 showing an equivalent circuit to FIG. 2, R.sub.1 : the combined resistance of each of ON resistances R.sub.P1 and R.sub.N1 in each of MOS transistors T.sub.P1 and T.sub.N1 forming the transmission gate TR
R.sub.P2 : the ON resistance of a MOS transistor T.sub.P2 PA1 R.sub.P3 : the ON resistance of a MOS transistor T.sub.P3
and the point A of the RAM cell was placed in the high level while the bit line L was placed in -V voltage by charging the inherent capacitance CB.
Since the point A had the high voltage, it was normal for such a high level at the point A to be transmitted to the bit line L. However, transmission of this high level was prevented because of the relationship between a reversed level of a second inverter circuit I.sub.n2 and the voltage -V.sub.A at the point A. That is, as indicated by the dotted lines of FIG. 2, the respective voltages were changed depending on their earlier conditions, to thereby destroy the voltage information stored in the RAM cell.
To prevent such a destruction, it was necessary to satisfy the following relationship between an ON resistance R.sub.1 of the transmission gate TR and the two ON resistances R.sub.P2 and R.sub.P3 of the transistors T.sub.P2 and T.sub.P3 in the first inverter I.sub.n1. EQU R.sub.1 &gt;&gt;R.sub.P2 +R.sub.P3
Further, it was necessary to satisfy a similar relationship between the transmission gate TR and the two ON resistances R.sub.N2 and R.sub.N3 in the transistors T.sub.N2 and T.sub.N3 in the first inverter I.sub.n1.
These relationships would be achieved by lowering the respective ON resistances R.sub.P2, R.sub.P3, R.sub.N2 and R.sub.N3 of the MOS transistors T.sub.P2, T.sub.P3, T.sub.N2 and T.sub.N3, respectively. To this end, the sizes of the respective transistors became large to a disadvantageous extent. When the ON resistance R.sub.1 of the transmission gate TR became great, access time was increased which was also disadvantageous.
Conventionally, these factors were defined by considering what access time for the RAM was necessary and what sizes of the RAM were permitted. Therefore, a circuit design of the RAM cell was very complicated and even through this complicated circuit design, a suitable circuit was never obtained which desirably satisfied the both factors.